1. Field of the Invention
The present invention relates in general to redundancy row/column pretest circuits for a semiconductor memory device, and more particularly, to a pretest circuit for pretesting operating states of redundancy row/column cells of the semiconductor memory device using a redundancy test signal inputted through an additional redundancy test pad, to check faults thereof.
2. Description of the Prior Art
In a conventional repairing method, a normal operation test is performed at a wafer state to find faulty cells. If the faulty cells are found, they are substituted with redundancy row/column cells by redundancy row/column circuits. As a result, a die is obtained in which the faulty cells are repaired.
However, the above-mentioned conventional repairing method has a disadvantage in that faults may occur in the repaired cells because the redundancy row/column cells have a similar fault probability to that of normal cells. Also, because the faulty cells are repaired after the normal operation test, when the faults occur in the repaired cells, a laser repair operation and the accompanying test operation must be performed, resulting in unnecessary time consumption.